1. Field of the Invention
The present invention relates to a method for fabricating an integrated circuit. More particularly, the present invention relates to a method for fabricating a semiconductor device.
2. Description of the Related Art
Metal silicide has many advantages--high melting point, stability and low resistance. Thus, the salicide process is currently applied in the manufacturing process for very large scale integration (VLSI) and ultra large scale integration (ULSI) devices.
When integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. However, source/drain region resistance in metal oxide semiconductor (MOS) transistors simultaneously increases, and the polysilicon electrodes that form the MOS gates and wiring lines within semiconductor devices introduce undesirable resistance. In order to reduce resistance and RC delay time to improve the operating speed of a device, a self-aligned silicide (salicide) process is employed. Therefore, a response time or an operating speed of the whole device is increased by reducing the gate resistance and the junction resistance.
A typical implementation of a silicide on a polysilicon electrode or silicon substrate is known as a self-aligned silicide process. It is employed to reduce semiconductor device resistance. FIGS. 1A through 1B are schematic, cross-sectional views showing the progression of the conventional manufacturing steps for a self-aligned silicide.
Referring to FIG. 1A, a substrate 100 having a patterned gate 102 is provided, and a lightly doped source/drain region is formed in the substrate 100 by an ion implantation process. A liner layer and an insulation layer are formed over the substrate 100 in order. Next, a portion of the insulation layer is removed by an etching process to form a spacer 108 on sidewalls of the patterned gate 102. The spacer 108 is used as a mask, and then a heavily doped source/drain region is formed in the substrate 100 by an ion implantation process, wherein the heavily doped source/drain region and the lightly doped source/drain region together form a source/drain region 110. A metallic layer 112 for forming a silicide is deposited over the substrate 100, and then an annealing process is performed. The metallic layer 112 only reacts with the silicon of the gate 102 and the source/drain region 110 to form a silicide layer 114 and 116 after performing the annealing process. The unreacted metallic layer 112 is removed by selective wet etching, as shown in FIG. 1B. Since the whole process of forming the silicide layer 114 and 116 does not require a photolithography step, the process is called a self-aligned silicide.
As integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. Therefore, an undesired resistance occurs in the polysilicon gate. To reduce the undesired resistance of the polysilicon gate, the top surface of the spacer 108 is lower than the upper surface of the gate 102. A portion of the gate 102 sidewalls is exposed, so that the exposed surface of the gate 102 is increased. As a result, contact area of the gate 102 and the metallic layer 112 is increased to enhance a volume of the silicide layer 114, and the resistance of the gate 102 is thereby reduced.
Another typical manufacturing method for semiconductors is provided to improve the drawback mentioned above. FIGS. 2A through FIG. 2B are schematic, cross-sectional views showing the progression of the conventional manufacturing steps for a semiconductor spacer.
Referring to FIG. 2A, a substrate 100 having a gate 102 is provided, and a liner layer 104 is formed on the substrate 100. Then, an insulation layer 106 is conformally formed over the substrate 100. The insulation layer 106 is made of a material such as silicon nitride layer. Subsequently, a portion of the insulation layer 106 is removed by an anisotropic dry etching process, and then the insulation layer 106 remaining on sidewalls of the gate 102 is used as a spacer 108, as shown in FIG. 2B. For exposing a portion of sidewalls of the gate 102, an over-etching process is performed after the anisotropic dry etching process. As a result, the spacer 108 and the liner layer 104 are transformed into a spacer 108a and a liner layer 104a, respectively. A portion of the sidewalls of the gate 102 is exposed, so that the top surface of the spacer 108 is lower than that of the gate 102 upper surface as shown in FIG. 2C.
However, the thickness of the liner layer 104 formed on the substrate 100 is not uniform, and a portion of the substrate 100, which is covered by the thinner part of the liner layer 104, is exposed during the over-etching process. Damage easily occurs on the substrate 100 as shown in FIG. 2B. Moreover, reactive particles, such as argon, bombarding the spacer 108 rebound therefrom to a specific position on substrate 100, so that damage occurs during the dry etching process. The conventional method described above for forming the spacer 108 easily damages the substrate 100. As a result, the reliability of the whole device is decreased.